As integrated circuit technologies have advanced, the size of these devices has correspondingly decreased. In particular, as devices are reduced in scale to comply with ever-smaller packaging, tighter constraints are applied to their dimensions and spacings. In the case of resistors, these constraints can limit the performance of the resistor.
For example, in silicon-on-insulator (SOI) technologies, thickness constraints can impact resistor designs. In some cases, such as in partially depleted SOI (PDSOI) structures, fully depleted SOI (FDSOI) structures and/or extremely thin SOI (ETSOI) structures, thickness constraints on resistors in these structures can limit the current carrying ability of those resistors. Further, these thickness constraints can result in resistors filling a disproportionally larger area in order to meet the same reliability requirements.